DESIGN AND SYNTHESIS FOR DEEP LEARNING AND MULTILAYER NEURAL NETWORK ARCHITECTURE USING VHDL

Artificial neural networks are extended on the basis of brain structure. Like the brain, ANNs can recognize patterns, handle facts and figures and be trained. They are prepared by artificial neurons which employ the quintessence of genetic neurons. In the research work, we have considered the 8 inputs ANN signal which is multiplied with their corresponding weights. The hardware chip is designed to support the system functionality in Xilinx ISE 14.2 software. The designed chip is simulated with Modelsim 10.0 software for test cases. The designed chip is also synthesized on SPARTAN-3E FPGA using VHDL programming and device hardware and timing parameters are also analyzed for the functionality of the chip.