Published April 19, 2020 | Version v1
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Design and Verification of 4 X 4 Wallace Tree Multiplier

Creators

  • 1. Vedic School of VLSI Design

Description

The aim of this paper is to study 4x4 Wallace tree multiplier. In high
performance processing units & computing systems, multiplication of two
binary numbers is primitive and most frequently used arithmetic operation.
Wallace tree multiplier is area efficient & high speed multiplier. This paper
presents design and verification of Wallace tree multiplier. Design is carried out
in Xilinx ISE Design Suite 14.7 using Verilog HDL and verification is carried
out in Questa Sim 10.4e using System Verilog HVL environment.

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