Published January 14, 2018 | Version v1
Conference paper Open

Multi-Dimensional LUT-based Digital Predistorter for Concurrent Dual-Band Envelope Tracking Power Amplifier Linearization

Creators

  • 1. Universitat Politècnica de Catalunya (UPC)
  • 2. Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)

Description

This paper presents a multi lookup table (LUT) implementation scheme for the 3D distributed memory polynomial (3D-DMP) behavioral model used in Digital Predistortion (DPD) linearization for concurrent dual-band envelope tracking (ET) power amplifiers (PAs). The proposed 3D-Distributed Memory LUTs (3D-DML) architecture is suitable for efficient FPGA implementation. In order to optimize the linearization performance as well as to reduce the number of resources of the 3D-DML model, a new variant of the Orthogonal Matching Pursuit (OMP) algorithm is proposed to properly select the best LUTs. Experimental results show that the proposed strategy reduces the number of LUTs (i.e. the number of coefficients) while meeting the targeted linearity levels.

Notes

Grant numbers : Aether (TEC2014-58341-C4-4-R).© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

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