Design and Implementation of Low Power Ring and Johnson Counter using Transistor Resizing Technology by VHDL
Creators
- 1. M.Tech Scholar,Department of Electronics & Communication Engineering Patel College of Science & Technology, Indore, MP, India
- 2. Assistant Professor,Department of Electronics & Communication Engineering Patel College of Science & Technology, Indore, MP, India
Description
In SOC’s (System on Chip), numerous systems have been utilized to decrease the dynamic power of by and the large circuit which forces physical limitations or depends intensely on rationale capacity of the circuit. Dynamic power is primarily devoured by clock organize. So methods to lessen the power in clock arrange really limit the dynamic power altogether.There is a prerequisite of supplanting the flip-flop with a more proficient circuit which has same usefulness while accomplishing low power, zone, and vigor to PVT varieties. The pulsed latch system is a standout amongst the most doable answers for this issue. In this work, the execution of the ring counter is enhanced utilizing a pulsed latch method. In rapid and low power VLSI applications where overwhelming pipelining is utilized, there is a necessity of low power edge activated flip-flops. The relocation from flip-flop to pulsed latch has turned out to be an incredible accomplishment in low power VLSI application.The design will be replicated and blended in Xilinx 14.1i ISE.
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Additional details
References
- 1. Tanushree Doi and Vandana Niranjan, "Low power and high performance ring counter using pulsed latch technique", 2016 International Conference on Micro-Electronics and Telecommunication Engineering.
- 2. Liaqat Moideen Parakundil and N. Saraswathi, "Low Power Pulse Triggered D-Flip Flops using MTCMOS and Self-Controllable Voltage Level Circuit", 2014 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT).
- 3. Dennis land Larsen, Pere Llimos Muntal, Ivan H. H. Jørgensen and Erik Bruun, "High-voltage Pulse-triggered SR Latch Level-Shifter Design Considerations", IEEE.
- 4. Jin-Fa Lin, "Low-Power Pulse-Triggered Flip-Flop DesignBased on a Signal Feed-Through Scheme", IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE.
- 5. Guang-Ping Xiang, Ji-Zhong Shen, Xue-Xiang Wu and Liang Geng, "Design of a Low-Power Pulse-Triggered Flip-Flop with Conditional Clock Technique", IEEE.
- 6. Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol and Jean-Didier Legat, "Design of a Robust and Ultra-Low-Voltage Pulse-Triggered Flip-Flop in 28nm UTBB-FDSOI Technology", 978-1-4799-1361-9/13/$31.00 ©2013 IEEE.
Subjects
- Electrical Engineering
- http://matjournals.com/Journal-of-Electrical-and-Power-System-Engineering.html