VERIFICATION APPROACH USING UVM

Verification is one of the most important activity in the flow of ASIC/VLSI design. Verification consu mes large amount of design flow cycle & efforts to ensure des ign is bug free. Hence it becomes intense requireme nt for powerful and reusable methodology for verification. The Universal Verification Methodology (UVM) is a powerful verification methodology that was architec ted to be able to verify a wide range of design siz es and design types. UVM is derived from other methodology like VMM,OVM,eRM. It is useful to verify designs in any langua ge like verilog,VHDL,System Verilog. Reusable verifi cation environment is possible using UVM & hence sa ving considerable time in Verification cycle. This paper talks about the architecture of environment using UVM. It also focuses on terms & ways used in Verification u sing UVM.

https://www.ijiert.org/paper-details?paper_id=140467