Design and Implementation of Shared Bus based Heterogeneous MPSoC

An MPSoC architecture is proposed with shared bus interconnect and its components mainly comprising of soft IPs. The proposed MPSoC architecture has four masters and four slaves communicated over a shared bus interconnect. Each master deals with two 16-bit inputs and process among an output of 32-bit. The slaves are four independent RAM soft IPs to be designed to handle 32-bit data. The main theme is to make the four masters and four slaves to get their tasks accessed through a 32-bit shared bus interconnect. Initially the soft IPs of processors and RAM memory elements are to be designed and to be verified using Modelsim simulation software. Before developing the proposed architecture, a prototype of one master to four slaves (1:4) with a simple address decoding scheme has to be developed and simulated in Modelsim simulation software. The prototype model architecture should be synthesized under target device Altera Cyclone II using Quartus synthesizing tool. The proposed architecture of 4 masters and 4 slaves with a common shared bus interconnect should be achieved and implement the entire architecture over Altera FPGA board and verify its functionality.