Design of an Advanced PLL for Accurate Phase Angle Extraction Under Grid Voltage Harmonics/Interharmonics and DC Offset

The presence of dc offset and harmonics/interharmonics in grid voltage input signal of phaselocked
loop (PLL) results in inaccurate controller response. The inaccuracies are due to the low and high
frequency oscillations that appear in the PLL estimated phase, amplitude and frequency. The importance of
DC offset and harmonic/interharmonic rejection capability for PLLs can be appreciated by international
standards that impose strict limitations for grid-tied converters. The suppression of fundamental frequency
oscillations caused by DC offset in the input signal must be carried out without compromising the dynamic
response of the system. The use of low pass filters for example results in undesirable, slow response. This
paper proposes an accurate and fast decoupling of fundamental frequency oscillations using a mathematic
cancellation decoupling cell. Higher frequency oscillations generated by harmonics/interharmonics are
eliminated by a different compensation network (HCN) that is also proposed in this paper. The performance
of conventional techniques is limited because they eliminate only specifically selected harmonics. The
proposed HCN module, however, eliminates any number of harmonics/interharmonics present in the grid
with the least computational complexity and without any prior knowledge. Furthermore, its advanced
features provide accurate synchronization under any abnormal grid condition at the lowest computational
complexity when compared to existing state-of-the-art PLLs. The advanced performance of the proposed
Harmonic-Interharmonic-DC-Offset (HIHDO) PLL is verified through simulation and experimental results.