Published September 1, 2013
| Version 17103
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Design and Implementation of a 10-bit SAR ADC
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Description
This paper presents the development of a 38.5 kS/s 10-bit low power SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and SAR digital logic to create 10 effective bits while consuming less than 7.8 mW with a 3.3 V power supply.
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References
- http://www.maximintegrated.com/app-notes/index.mvp/id/1080.
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- T. Xingyuan, C. Jianming, Z. ZHangming and Y. Yintang, "A high performance 90 nm CMOS SAR ADC with hybrid architecture," Journal of Semiconductors, vol. 31(1), Jan. 2010.
- W.-K. Chen, Linear Networks and Systems (Book style). Belmont, CA: Wadsworth, 1993, pp. 123–135.
- Weibin Wu, Tiansheng Hong et al., "Design and Implementation of SAR ADC," Journal of Computers, vol. 6, No.12, Dec. 2011.
- P. E. Allen & D. R. Holberg, "CMOS Analog Circuit Design," 2nd. ed. New York, Oxford University Press, 2002.