Journal article Open Access
Yukinari Minagi; Akinori Kanasugi
This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. The proposed arithmetic circuit performs floating-point arithmetic which is frequently used in science and technology. The data format is floating-point based on IEEE754. The proposed circuit is designed using VHDL, and verified the correct operation by simulations and experiments.
A. Kanasugi, A. Tsukahara, "A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory", Journal of Convergence Information Technology, vol.2, no.1, pp. 4-15, 2007.
A. Tsukahara, A. Kanasugi, "Genetic Algorithm with Dynamic Variable Number of Individuals and Accuracy", International Journal of Control, Automation, and Systems, vol. 7, no. 1, pp.1-6, 2009.
H. Shimada, Y. Hayakawa and A. Kanasugi, "An Architecture of Dynamically Reconfigurable Arithmetic Circuit", Proc. of 2009 Int. Conf. on Electronics Packaging, pp.963-966, 2009.
IEEE Std. 754 - 1985, IEEE Standard for Binary Floating-Point Arithmetic, IEEE, 1985.
M J. Myjak, J. G. Delgado-Frias, "A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance", IEEE Trans. on VLSI Systems, vol.16, no.1, pp.14-23, Jan 2008.
MIPS Technologies, Inc., MIPS32 Architecture for Programmers Volume I: Introduction to the MIPS32 Architecture, July 1, 2005.
T. J. Todman, et al, "Reconfigurable computing: architectures and design methods", IEE Proc.-Computers & Digital Techniques, vol. 152, no. 2, pp. 193 - 207, 2005.
T. Sato, H. Watanabe, K. Shiba, "Implementation of dynamically reconfigurable processor DAPDNA-2", VLSI Design, Automation and Test, 2005 IEEE VLSI-TSA International Symposium, pp. 323-324, 2005.
Xilinx, Inc., ML401/ML402/ML403 Evaluation Platform User Guide UG080 (v2.5), May 2006