Explainable Port Mapping Inference with Sparse Performance Counters for AMD's Zen Architectures (Artifact)

Performance models are instrumental for optimizing performance-sensitive code.
When modeling the use of functional units of out-of-order x86-64 CPUs, data availability varies by the manufacturer:
Instruction-to-port mappings for Intel's processors are available, whereas information for AMD's designs are lacking.
The reason for this disparity is that standard techniques to infer exact port mappings require hardware performance counters that AMD does not provide.

In this work, we modify the port mapping inference algorithm of the widely used uops.info project to not rely on Intel's performance counters.
The modifications are based on a formal port mapping model with a counter-example-guided algorithm powered by an SMT solver.
We investigate in how far AMD's processors comply with this model and where unexpected performance characteristics prevent an accurate port mapping.
Our results provide valuable insights for creators of CPU performance models as well as for software developers who want to achieve peak performance on recent AMD CPUs.

This artifact includes a prototype implementation of the proposed port mapping inference algorithm, written in python and using the z3 SMT solver.
It further provides the data sets and results of the Zen+ case study.
Our suggested artifact evaluation workflow focuses on evaluating the inferred port mapping for the Zen+ microarchitecture as provided in the artifact, including a reproduction of the quantitative evaluation of the paper.

We provide the artifact as a public repository on Github and as an archived virtual machine image bundled with all software dependencies that can be run using Vagrant and VirtualBox.
The virtual machine is based on Debian 12.4 and requires an x86-64 host system.
As our suggested artifact evaluation workflow does not include running actual microbenchmarks on a target system or executing the computationally expensive inference algorithm on realistic workloads, any contemporary x86-64 development machine suffices for evaluating the artifact.

This is an Artifact for ASPLOS 2024 (Fall)