NEW METHODOLOGY FOR LOW POWER HIGH SPEED CLA

Historically, VLSI designers have focused on increasing speed and reducing the area of digital systems. Low power design reduces cooling cost is and increases reliability especially for high density systems. Moreover,it reduces the weight and size of portable devices.Yet,high performance is still the main criterion for most digital systems, which may not be sacrificed to achieve low power dissipation.This study covers two logic families; namely CMOS and CPLpresents low power digital VLSI design methodologies.To verify the qualitative analysis, three gates AND, OR, MUX are implemented using two  logic families:CMOS,CPL.On the block level, a 16 bit CLA adder is used as a test vehicle to evaluate the performance of the above logic families.Then the factors like performance, Power of different CMOS logic styles is then analyzed and simulated. A 16bit CLA adder is designed,simulated, using 0.6µm CMOS technology.