PERFORMANCE ANALYSIS OF DIFFERENT N-BIT ADDERS USING REVERSIBLE LOGIC ON FPGA BOARD USING CHIPSCOPE

In current scenario, high-performance chips releasing large amounts of heat impose practical limitation. Reversible circuits that conserve information, by uncomputing bits instead of throwing them away. Reversible logic design attracting more interest due to its low power consumption. The paper gives brief idea to build variety of n-bit adders like Ripple carry adder, Carry look ahead adder, Carry save adder, Carry skip adder and Carry select adder circuits using the basic reversible gate like Peres gate, TSG, MTS, Taffoli, HNG etc. The designed adders are verified using chipscope on FPGA platform and compared w.r.t quantum cost, ancilla input, number of gates used and garbage outputs. Among these ripple carry adder and carry look ahead adder are efficient interms of garbage output and number of gates used. These adders can be used to build more complex circuits like ALU design.