Thermal impact of solder voids in the electronic packaging of power modules

In power electronic modules which are used in automotive industry, improving the cooling system is a challenging problem. In operation mode, the electric current causes an increase of the module’s temperature which can have an impact on it’s robustness and reliability. The dissipation of heat depends on the quality of the solder joint, which can present some porosity due to the chosen alloy and/or manufacturing process. In this work, we focus on the impact of solder defects (porosity) on the maximum temperature of the silicon chip. Static thermal analysis was performed using ANSYS code which is based on Finite Element Method (FEM). Results show an increase of maximum temperature along with the increase of the defect’s size (for cylindrical or prismatic void topology). Maximum temperature is controlled by the largest defect in the case of several defects, resulting in localized hot spots. In order to compare calculations to experimental research, maximum temperature evolution versus porosity is plotted.