PERFORMANCE ANALYSIS OF A LOW-POWER HIGH-SPEED HYBRID 1-BIT FULL ADDER CIRCUIT AND ITS IMPLEMENTATION

In this paper, a hybrid low power and high speed 1-bit full adder design employing both complimentary  metal  oxide (CMOS)  logic and transmission gate logic is reported. The design was implemented for 1 bit. The circuit was implemented using Mentor tanner tool in 180 and 90  nm technology. Performance parameters such as power, delay and transistor count were compared with existing designs such as complimentary pass transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS logic output drive full adder , and so on. For 1.8-V supply at 180-nm technology, the average power consumption (0.40893 uW) was found to be extremely low with moderately low delay (7.0975 ps) resulting from the incorporation of  strong transmission gates. Corresponding values of the same were 0.1265uW and 13.439ps at 90-nm technology operating at 1.2-V supply voltage.. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed. The design was further extended for implementing 2 bit multiplier also as an application of our proposed design