The NEORV32 RISC-V Processor

• [TRNG] software can now retrieve FIFO size by @stnolting in https://github.com/stnolting/neorv32/pull/616
• [DMA] add automatic trigger mode by @stnolting in https://github.com/stnolting/neorv32/pull/618
• 🐛 [linker script] fix section continuity issue by @stnolting in https://github.com/stnolting/neorv32/pull/626
• [SYSINFO] re-arrange bits by @stnolting in https://github.com/stnolting/neorv32/pull/627
• ✨ Re-add simplified stream link interface (SLINK) by @stnolting in https://github.com/stnolting/neorv32/pull/628
• :sparkles: add CRC unit by @stnolting in https://github.com/stnolting/neorv32/pull/632
• [makefile] extend GDB target by @stnolting in https://github.com/stnolting/neorv32/pull/634
• ⚠️ remove BUSKEEPER's status register by @stnolting in https://github.com/stnolting/neorv32/pull/635
• optimize CPU's control logic by @stnolting in https://github.com/stnolting/neorv32/pull/636
• 🧪 VHDL - use entity instantiation by @stnolting in https://github.com/stnolting/neorv32/pull/637

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.5...v1.8.6