Published May 18, 2023
| Version v1.8.5
Software
Open
The NEORV32 RISC-V Processor
Authors/Creators
Description
What's Changed
- ✨ add optional direct memory access controller (DMA) by @stnolting in https://github.com/stnolting/neorv32/pull/593
- [rtl] minor edits by @stnolting in https://github.com/stnolting/neorv32/pull/599
- 🐛 [rtl] fix bug in DMA by @stnolting in https://github.com/stnolting/neorv32/pull/601
- [rtl] minor edits; update to VUnit v5 by @stnolting in https://github.com/stnolting/neorv32/pull/605
- [rtl] rework SoC bus system by @stnolting in https://github.com/stnolting/neorv32/pull/607
- [rtl] minor rtl updates by @stnolting in https://github.com/stnolting/neorv32/pull/608
- 🐛 [FPU] fix bug in FPU trap handling by @stnolting in https://github.com/stnolting/neorv32/pull/609
- [CPU] move instruction address to mtval on ebreak exception by @stnolting in https://github.com/stnolting/neorv32/pull/611
- Add programmable TRNG interrupt by @stnolting in https://github.com/stnolting/neorv32/pull/615
Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.4...v1.8.5
Notes
If you use this project, please cite it as below.
Files
stnolting/neorv32-v1.8.5.zip
Files
(6.2 MB)
| Name | Size | Download all |
|---|---|---|
|
md5:4ef903e2d05bb51a5dfbb76d31fbccbf
|
6.2 MB | Preview Download |
Additional details
Related works
- Is supplement to
- https://github.com/stnolting/neorv32/tree/v1.8.5 (URL)