RISC-V CO-PROCESSOR UNIT FOR IMNPU SPECIFICATIONS, FUNCTIONAL SAFE RISC-V HOST CORE SPECIFICATIONS

The objective of deliverable 3.1 (D3.1) “RISC-V co-processor unit for IMNPU specifications, functional safe RISC-V host core specifications” is to define and provide the specifications of the two RISC-V based components in the NeuroSoC system:
- the RISC-V co-processor unit for IMNPU (RISC-V element with pink background halo inside the Neural Processing Unit (NPU) cluster,
- and the functional safe RISC-V host multi-core .
As implied in their names, both components are based on the RISC-V open Instruction Set Architecture (ISA) specifications as defined by RISC-V International. The RISC-V co-processor will provide a programmable inference accelerator directly embedded in the NPU cluster along the project developed Analog In-Memory Compute (AIMC) components. The RISC-V host multi-core component will provide a RISC-V multi-core enhanced with functional safety features as main control element of the NeuroSoC system. Sections II and III present these components in further detail. Deliverable D3.1 is the first deliverable of WP3 "Architecture". The produced specifications will serve as guidelines for the developments in T3.2 "Design of AI specialized RISC-V based local  digital processing unit for the IMNPU" and T3.3 "Design of a functional safe RISC-V multicore". Furthermore, D3.1 will serve to  prepare the integration of the RISC-V based components in the NPU cluster and the NeuroSoC processor, respectively in tasks T3.1 "Design of multi-tile mixed-signal IMNPU unit" and T3.4 "Design and integration of the NeuroSoC top level architecture (IMNPU, host processor, SoC IPs)". Finally, this deliverable will serve as input for the work developed inWP4 "Algorithms, Tools &Software", particularly for tasks T4.1 "Exploration of AI optimized ISA extensions" and T4.5 "Software stack and Linux porting on the host processor".