The NEORV32 RISC-V Processor

• [docs] add note about platform specific DTMs by @NikLeberg in https://github.com/stnolting/neorv32/pull/482
• 💄 [docs] update/rework figures by @stnolting in https://github.com/stnolting/neorv32/pull/483
• [rtl] Cleanup CPU interrupt controller by @stnolting in https://github.com/stnolting/neorv32/pull/484
• [rtl] rework mip csr by @stnolting in https://github.com/stnolting/neorv32/pull/486
• [rtl] CPU control optimization by @stnolting in https://github.com/stnolting/neorv32/pull/487
• [rtl] CPU: use record as main control bus type by @stnolting in https://github.com/stnolting/neorv32/pull/489
• [rtl] add co-processor timing monitor by @stnolting in https://github.com/stnolting/neorv32/pull/490
• [sw/lib/include/neorv32.h]: remove redundant uart typedef by @akaeba in https://github.com/stnolting/neorv32/pull/493
• ⚠️ Replace IO_GPIO_EN generic by @stnolting in https://github.com/stnolting/neorv32/pull/491
• [rtl] minor trap logic optimizations and fixes by @stnolting in https://github.com/stnolting/neorv32/pull/497
• Add run.py dump of VHDL-LS library mapping by @kraigher in https://github.com/stnolting/neorv32/pull/494
• [sw] add '_zicsr' to default MARCH configuration by @stnolting in https://github.com/stnolting/neorv32/pull/496
• 🐛 [rtl] fix bug in co-processor monitor by @stnolting in https://github.com/stnolting/neorv32/pull/500
• ⚠️ constrain & relocate PWM module by @stnolting in https://github.com/stnolting/neorv32/pull/501
• :warning: remove SLINK module by @stnolting in https://github.com/stnolting/neorv32/pull/502

• @NikLeberg made their first contribution in https://github.com/stnolting/neorv32/pull/482
• @kraigher made their first contribution in https://github.com/stnolting/neorv32/pull/494

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.0...v1.8.1