Design and Implementation of UART Serial Communication Module Based on FPGA

Designing a System–on-a-Chip (SoC) on the FPGA
is now a trend in digital design because it gives a lot of
advantages over discrete electronic based product such as higher
speed, lower power consumption, smaller size, lower cost etc.
UART (universal asynchronous receiver and transmitter) is a
serial communication protocol. Basically this protocol is used to
permit short distance, low cost and reliable full duplex
communication. It is used to exchange data between the
processor and peripherals. For reliable data transmission, serial
communication is very effective than parallel communication
when considering the cost as well as complexity of the system
increases. To design a UART which is implemented with Verilog
HDL can be easily integrated onto FPGA to achieve more
reliable and error free data transmission. This paper presents the
hardware implementation of UART using Verilog HDL on
FPGA:EP2C20F484C7, family of Altera cyclone II. Simulation is
done by Quartus II simulator which is fully compatible with
UART.