Design of 224/448 Gbps Nrz/Pam4 Wireline Transmitter Using 28Nm CMOS- and 250Nm InP-Technology

The global data traffic, whether wired or wireless, will not stop growing. The worldwide fixed internet traffic is increasing by 2-fold every 3-4 years. Therefore, faster optical communication systems are demanded for the transmission of larger volumes of data.
A typical digital coherent optical communications system contains digital-to-analog converter (DAC) to convert digital signals from digital signal processors (DSPs) to analog signals. These DACs are generally fabricated in the complementary metal oxide semiconductor (CMOS) process for integration with DSPs fabricated in the same process. Nowadays, CMOS DACs are facing speed bottlenecks due to their limited analog bandwidth of around 56 GHz, when used for high speed transmitter architectures targeting beyond 100 Gbps.
This PhD is exploring for solutions to overcome such bandwidth limitations to drive off-chip optical modulators with higher speeds. One of the solutions, which this PhD research is investigating, is to combine CMOS technology with a faster III-V technology namely Indium-Phosphide (InP). That is, all complex architectures like PRBS15, delay-blocks, duty-cycle correction (DCC) circuits and predistortion techniques like feed-forward equalization (FFE) and PAM4-level adjustments were implemented in 28nm planar CMOS to leverage from its high yields. Then, to extend the bandwidth and to target higher speeds, a 4:1-Analog Multiplexer (AMUX) was implemented in 250nm InP-DHBT technology.
Next, it is planned to combine this 4:1-AMUX with the aforementioned CMOS DACs such that speeds beyond 224 Gbaud symbolrates are achieved with 400mVpp output voltage swing. A further feature this 224/448 Gbps NRZ/PAM4 wireline CMOS-InP-transmitter module offers is the capability to equalize not only the channel of the CMOS DACs' output, but also the channel at the output of the first InP 2:1-AMUX to maintain signal integrity.