An n-input nth-order cross correlator firmware FPGA implementation
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Description
This work is a Verilog firmware for FPGAs of an auto-crosscorrelator with an ASCII protocol.
Up to 256 input lines are possible and relative baselines and baseprisms up to the 256nth order. It is possible to setup a device with the input lines number, output leds and multiplexer lines. A simple ASCII serial protocol can configure both the delay on each autocorrelated and crosscorrelated input or setup the output led lines and the crosscorrelation order as well.
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Additional details
Related works
- Is supplement to
- https://github.com/ahp-electronics/xc-firmware/tree/v2.4 (URL)