Implementation of a Visible Light Communications testbed in FPGA

Dedicated software defined testbeds for communication systems performance evaluation presents many advantages over using standard laboratory equipment, providing high reconfigurability and custom features design. This paper presents an FPGA-based implementation for visible light communications
(VLC) systems with multiband carrierless amplitude and phase (m-CAP) modulation. In this work, a Digilent Eclypse Z7 development board was used, along with DAC and ADC daughterboards. Concerning the hardware design, the blocks data generation, m-CAP modulation, carrier generation, receiver synchronism, and bit error rate (BER) analyzer were designed using the Xilinx System Generator tool. The implementation includes a ARM microprocessor for data acquisition and the testbed configuration,
using UART communication with a MatLab script. The testbed was experimentally validating using the target VLC system, and the results show the VLC system performance in terms of BER and symbol constellations, acquired with the testbed.