MOSFET mismatch characterization made easier: A 2-Transistor test array structure for a voltage-only measurement approach

Abstract: MOSFET mismatch measurements and characterization are repetitive tasks that require a huge amount of measurements, testing time, and data post-processing. In this presentation, an array test structure and a measurement method are proposed. They extraordinarily improve mismatch measurement time with a reduced equipment setup, while maintaining a high statistical confidence level. The structure is based on the combination of two stacked MOS transistors and the measurement methodology relies on just two single DC voltage measurements. With a theoretical speed improvement of 30x, the method enables fast extraction of MOSFET mismatch parameters, useful to designers, such as AVTH and Aβ with less than 2% error. The data correlation coefficient between the traditional and the proposed method is not less than 0.94, obtained in bulk CMOS test chips, thus confirming the high statistical confidence of the extraction method.