IMPROVEMENT IN NOISE AND DELAY IN DOMINO CMOS LOGIC CIRCUIT

New    experiments are always welcomed in the field of chip designing in VLSI technology. VLSI is advanced innovation   over solid   state devices and is based on CMOS designing. CMOS is a combination   of   PMOS and NMOS. The CMOS technology   is mostly used to reduce power dissipation in circuitry and to minimize the losses. Still a sufficient amount of noise is present, which   can cause for distortion in transmitted signal and make the whole transmission spurious.

There are some known techniques which are used to minimize noise in any circuit i.e. keeper technique, pre-charge internal nodes and NMOS pull up transistor. The improvement over these three techniques is required so that noise could be more minimized and performance of circuitry can be increased. In this paper, experiments are done to add an additional part in the circuit to minimize the noise. The new improved circuit is named as ‘HIGH SPEED MASTER OUTPUT KEEPER DOMINO TECHNIQUE’ which minimize the noise up to great extent. All the experiment and calculations are done for logic gate using Tanner Tool EDA.  The lowest noise present in AND gate was 1.75407 NV/HZ in old technique while it is minimize to 1.40310 NV/HZ in new technique.