Published October 24, 2021 | Version v1
Dataset Open

Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference [Artefact Evaluation]

Authors/Creators

  • 1. Imperial College London
  • 2. Cornell University

Description

Source code of paper "Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference" submitted to FPGA'22 for artefact evaluation.

Files

artifact_evaluation.zip

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