Published June 30, 2020 | Version v1
Journal article Open

The Influence of Gate Bias on the Anneal of Hot-Carrier Degradation

Authors/Creators

  • 1. ESAT, KU Leuven, Leuven, Belgium
  • 2. IMEC

Description

We observe that non-zero gate bias applied during a high temperature anneal following hot-carrier degradation (HCD) impacts degradation recovery in nFETs. The devices are arranged into custom-built arrays and fabricated in a commercial 40 nm bulk CMOS technology and the FET anneal is induced by on-chip poly-Si heaters. The anneal is modeled using Stesmans' passivation model for Pb-defects in hydrogen gas (H2). Negative gate bias improves the anneal, in line with studies on biased passivation of process-induced Pb-defects.

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Additional details

Funding

European Commission
MoCRIV - Modeling critical reliability issues in VLSI technologies beyond 2020 794950