A Unified Approach for Performance Degradation Analysis from Transistor to Gate Level

In this paper, we present an extensive analysis of the performance degradation in MOSFET
based circuits. The physical effects that we consider are the random dopant fluctuation
(RDF), the oxide thickness fluctuation (OTF) and the Hot-carrier-Instability (HCI). The
work that we propose is based on two main key points: First, the performance degradation
is studied considering BULK, Silicon-On-Insulator (SOI) and Double Gate (DG) MOSFET
technologies. The analysis considers technology nodes from 45nm to 11nm. For the HCI effect
we consider also the time-dependent evolution of the parameters of the circuit. Second,
the analysis is performed from transistor level to gate level. Models are used to evaluate the
variation of transistors key parameters, and how these variation affects performance at gate
level as well.The work here presented was obtained using TAMTAMS Web, an open and
publicly available framework for analysis of circuits based on transistors. The use of TAMTAMS Web greatly increases the value of this work, given that the analysis can be easily
extended and improved in both complexity and depth.