Low-latency machine learning inference on FPGAs
- 1. University of California San Diego
- 2. Fermi National Accelerator Laboratory
- 3. MIT
- 4. CERN
- 5. University of Washington
- 6. University of Illinois at Chicago
- 7. HawkEye 360
Description
Machine learning methods are ubiquitous in particle physics and have proven to be very performant. One unique application within particle physics is the FPGA-based trigger and data acquisition systems that require sub-microsecond latencies and specialized hardware. Accelerating these algorithms in low-latency specialized hardware, such as FPGAs, is also of great interest in many scientific fields. Development of machine learning algorithms on these systems has historically been difficult due to the specific expertise required to program FPGAs. We present a compiler based on High-Level Synthesis (HLS) called hls4ml to build machine learning models in FPGAs The use of HLS increases accessibility across a broad user community and allows for a drastic decrease in firmware development time. We demonstrate the effectiveness of this tool by synthesizing fully-connected neural networks of varying sizes and bit precisions. We then explore the required design space needed to map out the FPGA resources and latency.