Published November 27, 2019
| Version 1.0.0
Conference paper
Open
No RISC, no Fun: Comparison of Hardware Accelerated Hash Functions for XMSS
Authors/Creators
- 1. Department of Computer Science, University of Applied Sciences Wiesbaden, Germany
Description
SHA-3.tar.gz : Bundle including a VexRiscv-CPU implementation (based on https://github.com/SpinalHDL/VexRiscv) with a hardware accelerator for SHA-3, and software implementation of XMSS (https://github.com/XMSS/xmss-reference) for the given RISC-V-CPU.
SHA-256.tar.gz : Bundle including a VexRiscv-CPU implementation (based on https://github.com/SpinalHDL/VexRiscv) with a hardware accelerator for SHA-256, and software implementation of XMSS (https://github.com/XMSS/xmss-reference) for the given RISC-V-CPU.
Files
Files
(13.2 MB)
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md5:f11082c9fb266038610ab8890c223f44
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6.6 MB | Download |
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md5:9b99f219aa07445d3c4d77db8a99d522
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6.6 MB | Download |