DESIGN OF A LOW POWER CONSUMING SRAM CELL USING MINIMUM TRANSISTORS IN FINFET TECHNOLOGY

Power leakage in a RAM cell is a major concern in today’s development of shrinking size and high standby memories.  To solve the power leakage problem, many researchers have proposed different ideas from the device level to the architectural level and above. SRAM designs has become the issue of significant research to increase require for laptops, integrated circuit (IC) memory cards, notebooks and hand held communication devices. This article is based on the motivation of reduction of the average leakage power in SRAM memory cell in the 6T, 7T, 8T and 9T in FINFET technology at 22.5nm by using the Tanner tool which is having a supply voltage of 1.7 volts. The circuit verification is done on the Tanner tool, Schematic of the SRAM cell is designed on the S- Edit and net list simulation done by using T-spice and waveforms are analyzed through the W-edit.