Published November 11, 2026 | Version 1.0.0
Working paper Open

Self-Specializing Neuromorphic Computer: A Distributed Architecture Beyond the NPU

Authors/Creators

Description

A concept paper proposing a self-specialising neuromorphic compute architecture built from existing technologies.

Core ideas:

  • Hardware that specialises itself through use: a RISC core offloading work to reconfigurable logic and analog memristor crossbars.
  • Task training: specialisation through exposure to a varied class of related tasks, with checkpoints for rollback.
  • Routing learned from results: inter-cell routes weighted by accuracy, speed and round-trip time, giving self-organisation and self-healing.

Includes the motivation for departing from digital simulation of neural networks, related work, one illustrative implementation (component budget and power targets), and open questions for the community.

Shared to stimulate discussion rather than as a finished design. Feedback welcome.

Files

Self-Specialising Neuromorphic Compute A Distributed Architecture Beyond the NPU.pdf

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Additional details

Dates

Created
2026-11-06
Submitted
2026-11-11

References

  • M. Horowitz, "Computing's energy problem (and what we can do about it)" IEEE International Solid-State Circuits Conference, 2014
  • D. S. Modha et al., "Neural inference at the frontier of energy, space, and time," Science , vol. 382, 2023.
  • Intel, "Intel Builds World's Largest Neuromorphic System to Enable More SustainableAI," Intel Newsroom, April 2024. https://newsroom.intel.com/artificial-intelligence/intel-builds-worlds-largest-neuromorphic-system
  • S. Höppner et al., "The SpiNNaker 2 Processing Element Architecture for HybridDigital Neuromorphic Computing," arXiv:2103.08392, 2021; and SpiNNaker2 systemoverview, arXiv:2401.04491, 2024.
  • S. Ambrogio et al., "An analog-AI chip for energy-efficient speech recognition andtranscription," Nature , vol. 620, pp. 768–775, 2023.
  • M. Le Gallo et al., "A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference," Nature Electronics , 2023.
  • W. Zhang et al., "Edge learning using a fully integrated neuro-inspired memristor chip," Science , vol. 381, pp. 1205–1211, 2023.
  • R. Razdan and M. D. Smith, "A high-performance microarchitecture with hardware-programmable functional units," MICRO-27 , 1994.
  • J. R. Hauser and J. Wawrzynek, "Garp: a MIPS processor with a reconfigurablecoprocessor," IEEE Symposium on FPGAs for Custom Computing Machines (FCCM) ,1997.
  • "NVIDIA Rubin Enters Full Production: The 336 Billion Transistor GPU Reshaping AIInfrastructure," Introl, 2026. https://introl.com/blog/nvidia-rubin-full-production-ces-2026-ai-infrastructure
  • "Nvidia's new six-trillion transistor Vera Rubin 'superchip'… makes the 92-billiontransistor RTX 5090 gaming GPU look positively puny," PC Gamer.https://www.pcgamer.com/hardware/graphics-cards/nvidias-new-six-trillion-transistor-vera-rubin-superchip-for-ai-makes-the-92-billion-transistor-rtx-5090-gaming-gpu-look-positively-puny
  • "Nvidia GeForce RTX 5090" specifications, PC Gamer.https://www.pcgamer.com/nvidia-geforce-rtx-5090