LOW POWER VLSI-BASED EV CHARGING CONTROLLER

Electric-vehicle (EV) charging requires control logic that responds to a charging request and prevents charging when supplied safety-status signals indicate an unsafe condition. This paper presents a digital EV charging controller described in Verilog Hardware Description Language (HDL). The controller receives five inputs: start, voltage_ok, current_ok, battery_full, and fault. Its intended charging-permission condition requires an active start request, acceptable voltage and current status, a battery that is not full, and no active fault. The outputs are charge_enable, charging_complete, and fault_output. The design was developed and examined through simulation and Xilinx Vivado design reports. The reported synthesis result uses one Look-Up Table (LUT) and eight I/O resources; the estimated on-chip power is 0.073 W, with low confidence indicated in the power report. The work is a digital logic prototype and does not include a physical EV charging power stage or hardware safety validation.