Spin-Transfer Torque MRAM (STT-MRAM) and Spin-Orbit Torque (SOT) In-Memory Computing: Perpendicular Magnetic Anisotropy, Crossbar Arrays, and Deep Learning Accelerators

The insatiable memory bandwidth demands of deep learning foundation models and edge artificial intelligence 
are bottlenecked by the Von Neumann bottleneck: the continuous energy-prohibitive shuttling of weights and activations 
between off-chip dynamic RAM (DRAM) and processor arithmetic logic units (ALUs). Magnetoresistive Random Access 
Memory (MRAM), anchored by magnetic tunnel junctions (MTJs) exhibiting Perpendicular Magnetic Anisotropy (PMA), 
establishes a non-volatile, radiation-hardened, and virtually wear-out-free memory technology capable of high-density 
integration alongside sub-5nm CMOS logic. By exploiting Spin-Transfer Torque (STT) and emerging three-terminal Spin
Orbit Torque (SOT) switching mechanisms, MRAM enables ultra-fast write speeds (~ns) and zero standby leakage power. 
Furthermore, integrating MTJ crossbar arrays into non-volatile In-Memory Computing (IMC) architectures allows 
matrix-vector multiplications (MVM)—the dominant workload in neural network inference—to be executed natively inside 
memory via Ohm's and Kirchhoff's laws with sub-nanosecond latency and massive energy reduction. However, translating 
spintronic devices into production in-memory computing systems introduces severe physical and circuit bottlenecks: 
stochastic thermal switching jitter, limited tunneling magnetoresistance (TMR) ratios restricting multi-bit precision, IR
drop voltage drops across dense crossbar lines, and write-read disturbance errors. This paper presents an exhaustive, 
mathematically formal technical investigation and empirical benchmark of STT-MRAM and SOT-MRAM in-memory 
computing architectures. We formalize spin-transfer torque switching dynamics via the Landau-Lifshitz-Gilbert
Slonczewski (LLGS) equation, derive crossbar non-volatile dot-product transfer functions, and model stochastic thermal 
stability factors under PMA scaling. Furthermore, we construct an enterprise SPICE and hardware-in-the-loop testbed 
evaluating 64Mb STT-MRAM macro arrays and 3-terminal SOT-MRAM neuromorphic inference accelerators across 
Vision Transformers and ResNet workloads. Our empirical findings demonstrate that our SOT-MRAM in-memory 
accelerator achieves an energy efficiency of 142.6 Tera-Operations per Second per Watt (TOPS/W)—a 14x improvement 
over 4nm digital GPU SRAM caches—while sustaining a sub-nanosecond MVM latency and 98.4% image classification 
accuracy. Finally, we formulate open challenges in ultra-dense 3D vertical MTJ integration, all-spintronic non-volatile 
spiking logic, and quantum-resistant spintronic PUFs.