DDF-L05: RTL Module Architecture and Functional Simulation

 This lecture treats functional simulation not as a demonstration of attractive waveforms but
as a controlled, reproducible experiment on an RTL model. It covers hierarchy, testbench design, dis‐
crete-event time, safe clock/reset stimulus and sampling, reference models, automated checks, four-
state logic, VCD/FST tracing, diagnosis, and preservation of evidence. An eight-bit counter illustrates
the basic loop of requirement, stimulus, observation, oracle, and verdict. The four-sample moving-av‐
erage filter connects L05 to the completed DDF-LAB-01 system-model exercise and the architectural
decision discussed in L04. The scope of claims is explicit: SIM_PASS does not imply SYNTH_PASS, TIM‐
ING_PASS, or a real-hardware result.