FPGA-Accelerated Sub-Microsecond Union-Find Decoding for Real-Time Surface-Code Quantum Memory

Architecture manuscript. Latency, power, and resource figures are design estimates unless otherwise marked as measured. Related FPGA Union-Find implementations (Helios / Collision Clustering) are cited for comparison.

Abstract

Fault-tolerant quantum computation requires continuous decoding of stabilizer syndromes within cycle times that, for superconducting processors, are often 200 ns–1 μs. Host-processor decoders are subject to operating-system jitter, DMA overhead, and memory-hierarchy latency, which make deterministic sub-microsecond service difficult. This paper describes a fully pipelined FPGA architecture for a Union-Find decoder aimed at surface-code quantum memory. The pipeline integrates Aurora-based syndrome acquisition, streaming defect extraction, a path-halving Union-Find engine with hazard forwarding, localized peeling, and dual-port Pauli-frame updates. All latency-critical state is on-chip (BRAM, UltraRAM, distributed RAM). At a target clock of 400 MHz the design estimate for end-to-end latency is 170–390 ns below threshold, with a conservative worst-case bound near 500 ns—inside a 1 μs cycle. Memory for a decoding window scales as O(d³) with the space-time graph, not as O(d³) measurements per cycle. Power is estimated at 3–6 W per logical patch at the FPGA, which remains at room temperature. The contribution is a single deterministic pipeline that does not require a host CPU in the inner loop. It is an architecture and resource plan; it does not replace measured implementations such as Helios.

Keywords: surface code; quantum error correction; Union-Find decoder; FPGA; real-time decoding; Pauli frame; clock gating.

1. Introduction

Surface-code fault tolerance proceeds by repeated stabilizer measurement and classical decoding of the syndrome stream [1], [9], [10]. Superconducting cycle times commonly fall in T_cycle ~ 200 ns–1 μs [13]. Software decoders on CPUs or GPUs introduce scheduling jitter, DMA cost, cache misses, and synchronization [14]–[16]. Minimum-weight perfect matching (MWPM) is accurate but worst-case cubic in the number of defects and heavy for large distance [17], [18]. The Union-Find decoder of Delfosse and Nickerson is almost-linear and close to MWPM in accuracy, which makes it a natural hardware target [3].

FPGA and ASIC decoders have already shown that real-time surface-code decoding is possible. Das et al. gave a Union-Find micro-architecture; Liyanage et al. (Helios) implemented distributed Union-Find on a VCU129 up to d = 21 with mean times of order 10 ns per round under phenomenological noise, and a resource-optimized d = 51 point near 544 ns per round [14], [15]. Collision Clustering, another Union-Find variant, has been mapped to FPGA and ASIC with sub-microsecond times at large patch size [16]. The present manuscript specifies a single-tile, fully streaming pipeline—acquisition through Pauli frame—with explicit memory equations, banked Find ports, path-halving (not recursive compression), clock-enable power control, and a latency budget written against T_cycle = 1 μs. It is intended as a self-contained hardware architecture that can be implemented or compared against those measured designs.

2. System Architecture

The decoder is a fixed-depth pipeline. Stages are registered and advance on the same clock. After fill, a new syndrome frame can be accepted every cycle from the control layer; variable work inside Union-Find is bounded by a worst-case iteration budget, not by a host thread. Stages:

•    Syndrome acquisition and deserialization (Aurora 64B/66B over GTY).

•    Defect extraction unit (DEU): frame-to-frame XOR and sparse packing.

•    Pipelined Union-Find engine: growth, union, path-halving find, boundary test.

•    Localized peeling of cluster spanning forests.

•    Dual-port Pauli-frame memory toward the quantum controller.

No stage waits on a later stage. No latency-critical structure lives in DRAM or on a host.

3. Syndrome Acquisition and Deserialization

Stabilizer outcomes arrive serialized on multi-gigabit links. The link layer is Aurora 64B/66B, a low-overhead framing protocol with about 3% encoding cost, AXI4-Stream user ports, and support for GTY/GTYP/GTM on UltraScale+ and Versal [7]. The physical layer uses GTY transceivers with channel bonding. The receiver aligns the 64B/66B stream, descrambles, strips idles and control words, and deserializes a parallel syndrome frame whose width matches the stabilizer schedule. Aurora framing markers hold alignment; a CRC flags link errors. An elastic FIFO absorbs residual clock-domain difference. The deserializer is intended to emit one frame per T_cycle without a deep buffer.

4. Streaming Defect Extraction Unit

Decoding uses the syndrome change, not the raw bit [2], [11]:

d_k(t) = s_k(t) XOR s_k(t−1).

A one in d_k(t) is a space-time defect, an endpoint of an error chain in the decoding graph [11]. The DEU holds the previous frame in a register file, XORs all stabilizers in parallel, priority-encodes a sparse defect list, and pushes it to a FIFO. Below threshold the defect density is low and FIFO occupancy stays bounded [1], [11]. Boundary-adjacent stabilizers are tagged so cluster growth can terminate on the code boundary.

5. Pipelined Union-Find Engine

5.1 Cluster growth

The scheduler follows Delfosse–Nickerson [3]. Each defect starts as its own cluster. Clusters grow by taking half-edges, then neighboring edges, in the parity-check (space-time) graph. Meeting clusters merge. Growth stops when every cluster is even or touches a boundary. Growth and merge requests are issued at a fixed issue rate into the disjoint-set pipeline.

5.2 Disjoint-set representation

State is a parent array and a rank array. The primitives are Find(v) and Union(u, v). Weighted union keeps height logarithmic; path reduction keeps amortized cost nearly constant [4]. Together they underwrite the almost-linear sequential bound [3], [4].

5.3 Path-halving find

Recursive full compression has unbounded depth and is a poor FPGA citizen. The pipeline uses path halving: parent[v] ← parent[parent[v]]. This is a standard one-pass reduction with the same practical amortized cost [4]. Each iteration is a constant number of memory operations and maps to a fixed pipeline. Find ends when a root is reached or a bound on hops is hit (the bound is part of the worst-case latency contract).

5.4 Hazards and forwarding

Overlapping Union and Find on the same node are read-after-write hazards [19]. A small hazard unit stalls a fixed number of cycles or forwards a newly written parent past BRAM read latency. The unit operates on a bounded register set and does not make latency data-dependent beyond that fixed stall.

5.5 Localized peeling

After a cluster is valid, peeling walks its spanning forest and emits a correction chain that matches the defects in that cluster [3]. Peeling is local, so it can start on finished clusters while other clusters still grow. Edges from peeling become Pauli-frame writes.

6. Pauli Frame Management

Corrections are not forced as extra quantum gates on the device. They accumulate in a classical Pauli frame [5], [6], [22]:

P_frame ← P_frame XOR C_X.

The frame sits in dual-port distributed RAM: the decoder writes the current frame while the controller reads the previous one. Reads and writes are registered. No extra architectural latency is added past peeling.

7. Memory Architecture

Latency-critical state is on-chip:

M_UF = M_parent + M_rank + M_parity + M_boundary + M_edge.

With N vertices in the decoding graph: M_parent = N ceil(log2 N) bits; M_rank ≈ 4N bits; M_parity = N bits; M_boundary = N bits; M_edge = 2E bits.

Mapping follows the UltraScale+ / Versal memory hierarchy [20], [21]. UltraRAM is used for large edge tables (deterministic latency, high bits per column). Distributed RAM is used for the small, line-rate Pauli cache.

Parent accesses are striped: Bank(v) = v mod B, so several Finds can issue together. Arbitration is a fixed-priority encoder on the bank index. Bank selection is combinational from the node id.

8. Scalability

A distance-d surface-code cycle measures O(d²) stabilizers, not O(d³). The O(d³) figure belongs to the space-time decoding graph when the window depth w is taken of order d (w rounds × O(d²) checks). That is the N that enters M_UF. Per-cycle I/O remains O(d²). The earlier formula N_s = d²(d−1) as “measurements per cycle” is withdrawn; the table below is space-time volume for w = d, order-of-magnitude only.

Below threshold, active defects N_active ≪ N, so the FIFO and the scheduler visit neighborhoods, not the whole lattice [1], [11]. Multi-tile scaling replicates DEU, Union-Find, Pauli RAM, and a local FIFO per tile, with a light boundary mesh, consistent with modular decoder proposals [14]–[16].

9. Throughput and Latency Budget

Clock target: f_clk = 400 MHz, T_clk = 2.5 ns (4×10⁸ pipeline slots per second). Design estimate below threshold: 170 ns ≤ L_avg ≤ 390 ns. Worst case: L_max = L_fixed + N_c^max T_UF with L_fixed ≈ 45 ns for the front end, giving L_max ≈ 500 ns under a conservative cluster bound. That is less than T_cycle = 1 μs [13]. These numbers are budgets, not place-and-route measurements. Measured Union-Find FPGAs already report mean times from ~10 ns/round (Helios, small d, phenomenological) to hundreds of ns/round at large d [15], [16]; the present pipeline is specified to sit in that same real-time band.

10. Power and Thermal Placement

P_total = P_static + P_logic + P_memory + P_transceiver + P_clock. Single-patch estimate:

Sum ≈ 3–6 W at the FPGA. The FPGA stays at room temperature. Only the device and immediate control lines sit at millikelvin [13].

11. Clock-Enable Power Control

Dynamic power is α C V² f. The lever is activity α. The design uses FPGA clock-enables on registers (CE pins), not a chopped clock tree:

always @(posedge clk) if (ce) state <= next_state;

BRAM/URAM enable is RequestValid. A hierarchical controller watches FIFO occupancy, cluster count, in-flight Finds, and pending peels, and drives UF_EN, PEEL_EN, FRAME_EN. Large regions may use BUFGCE / BUFHCE [8]. Below threshold, clock-enable gating is estimated to cut average dynamic power by roughly 30–60% (illustratively 5 W → 2–3 W). Disabled stages restart on the next valid defect; the latency contract does not become data-dependent beyond the already-bounded pipeline.

12. Resource Estimate

This envelope fits mid-range UltraScale+ and Versal parts [21] and is in the same class as published FPGA decoders [14]–[16]. Exact use depends on d, window depth, and bank count.

13. Reliability

Long runs need BRAM ECC, configuration scrubbing, thermal sensors, watchdogs, and clock-failure detect [23]. Those are vendor-supported on SRAM FPGAs. They protect the pipeline against silent SEU and clock-tree glitches; they do not change the Union-Find algorithm.

14. Conclusion

A hardware Union-Find pipeline for surface-code memory can keep acquisition, defect extraction, disjoint-set growth, peeling, and Pauli-frame update on one FPGA, on-chip, with a latency budget inside 1 μs at 400 MHz. Memory follows the space-time graph, O(d³) when the window is order d. Power is a few watts at room temperature. The inner loop does not need a host processor.

What this manuscript is not: a replacement for measured Helios or Collision Clustering numbers, and not a claim that 170–390 ns has been closed in timing on a named part. The next step is RTL, place-and-route, and a syndrome-trace benchmark against those implementations at matched d, p, and window.

References

[1] A. G. Fowler, M. Mariantoni, J. M. Martinis, and A. N. Cleland, “Surface codes: Towards practical large-scale quantum computation,” Phys. Rev. A, vol. 86, no. 3, p. 032324, 2012.

[2] A. G. Fowler, D. S. Wang, and L. C. L. Hollenberg, “Surface code quantum error correction incorporating accurate error propagation,” Quantum Inf. Comput., vol. 11, pp. 8–18, 2011.

[3] N. Delfosse and N. H. Nickerson, “Almost-linear time decoding algorithm for topological codes,” Quantum, vol. 5, p. 595, 2021; arXiv:1709.06218.

[4] R. E. Tarjan, “Efficiency of a good but not linear set union algorithm,” J. ACM, vol. 22, no. 2, pp. 215–225, 1975.

[5] L. Riesebos, “Pauli frames for quantum computer architectures,” M.Sc. thesis, Delft University of Technology, 2016.

[6] D. Gottesman, “The Heisenberg representation of quantum computers,” arXiv:quant-ph/9807006, 1998.

[7] AMD, Aurora 64B/66B LogiCORE IP Product Guide (PG074) and Aurora 64B/66B Protocol Specification (SP011).

[8] AMD, UltraScale Architecture Clocking Resources User Guide (UG572).

[9] A. Yu. Kitaev, “Fault-tolerant quantum computation by anyons,” Ann. Phys., vol. 303, pp. 2–30, 2003.

[10] S. B. Bravyi and A. Yu. Kitaev, “Quantum codes on a lattice with boundary,” arXiv:quant-ph/9811052, 1998.

[11] E. Dennis, A. Kitaev, A. Landahl, and J. Preskill, “Topological quantum memory,” J. Math. Phys., vol. 43, no. 9, pp. 4452–4505, 2002.

[12] J. Edmonds, “Paths, trees, and flowers,” Canad. J. Math., vol. 17, pp. 449–467, 1965.

[13] Google Quantum AI, “Suppressing quantum errors by scaling a surface code logical qubit,” Nature, vol. 614, pp. 676–681, 2023.

[14] P. Das, C. A. Pattison, S. Manne, D. Carmean, K. Svore, M. Qureshi, and N. Delfosse, “A scalable decoder micro-architecture for fault-tolerant quantum computing,” arXiv:2001.06598, 2020.

[15] N. Liyanage, Y. Wu, S. Tagare, and L. Zhong, “FPGA-based distributed Union-Find decoder for surface codes,” IEEE Trans. Quantum Eng., vol. 5, 2024, doi:10.1109/TQE.2024.3467271; arXiv:2406.08491.

[16] B. Barber et al., “A real-time, scalable, fast and highly resource efficient decoder for a quantum computer,” arXiv:2309.05558; Nature Electronics related Collision Clustering implementation.

[17] J. Edmonds, “Maximum matching and a polyhedron with 0,1-vertices,” J. Res. Natl. Bur. Stand. B, vol. 69, pp. 125–130, 1965.

[18] V. Kolmogorov, “Blossom V: A new implementation of a minimum cost perfect matching algorithm,” Math. Prog. Comput., vol. 1, pp. 43–67, 2009.

[19] J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 6th ed. Morgan Kaufmann, 2017.

[20] AMD, UltraScale Architecture Memory Resources User Guide (UG573).

[21] AMD, Versal Adaptive SoC Technical Reference Manual (AM011) and UltraScale+ product tables.

[22] C. Chamberland, P. Iyer, and D. Poulin, “Fault-tolerant quantum computing in the Pauli or Clifford frame with slow error diagnostics,” Quantum, vol. 2, p. 43, 2018.

[23] AMD, Soft Error Mitigation (SEM) Controller LogiCORE IP Product Guide (PG187).