Design of a Low-Power RISC-V Microcontroller with An Integrated Neural Network Accelerator for Edge AI

Edge artificial intelligence has progressed to a point that neural-network inference requires microcontroller-class systems to run even less efficiently than before. This paper introduces a low-power 32-bit RISC-V microcontroller that integrates a compact INT8 neural network accelerator (NNA) for convolutional and fully connected neural network inferences. A RV32IMC host core, 128 KB of main memory (SRAM), a memory-mapped accelerator interface, a 32 KB local scratchpad, support for DMA (Direct Memory Access), 16 parallel INT8 multiply-accumulate (MAC) units, 32-bit accumulation, programmable requantization, ReLU activation, clock gating, and CPU sleep are all integrated in this design. Two workload classes in the MLPerf Tiny benchmark suite are used to evaluate the architecture-level design space. These classes include keyword spotting using a Depthwise Separable CNN (DS-CNN) based approach on the Speech Command dataset, and image classification using a compact ResNet-based approach on the CIFAR-10 dataset. Improving inference speed while consuming less power was the focus of this study. A lot of power is consumed when computations are performed, but many operations can be performed quickly. The design demonstrated a projected 9.42× speedup for keyword spotting and 12.77× for image classification, while also drawing 81.9% less power (for the keyword spotting benchmark) and 86.4% less power (for the image classification benchmark). This suggests that integrated RV32IMC and NNA architectures should be constructed to perform further FPGA and ASIC validation to test the implications on physical power and the overall system resource consumption.