Published August 19, 2026
| Version v1
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VXI16 Asymmetric Dual-Core Motor Machine Embedded Control Architecture
Authors/Creators
Description
Project Overview
The VXI16 Asymmetric Dual-Core Motor Machine Embedded Control Architecture is a high-performance, production-grade asymmetric multi-processing (AMP) firmware topology optimized for the dual-core STM32H747 microcontroller. This software provides the digital control backbone and real-time execution layers required to build, test, and safely operate high-power electrical machines driven by advanced Silicon Carbide (SiC) three-phase inverter topologies.
Architectural Layout & Core Allocation
The codebase utilizes a strict hardware-separated dual-core execution strategy to isolate critical real-time motor control loops from background communication stacks:
- Cortex-M7 Host Core (Supervisor): Operates as the master system orchestrator out of Flash Bank 1. It manages high-bandwidth bare-metal Ethernet DMA descriptor rings and serializes incoming Modbus protocol register frames via a clean C-linkage protocol parsing engine.
- Cortex-M4 Safety Core (Real-Time Motor Loop): Operates as an independent, deterministic execution engine out of Flash Bank 2 [ysD9J5]. Built using a high-efficiency C++ Unity Build layout, this core executes a tightly integrated field-oriented control (FOC) suite, space vector modulation (SVM) switching algorithms, deadtime compensation loops, and high-speed hardware fault matrices.
Key Software Capabilities
- Asymmetric Multi-Processing (AMP): Implements structured inter-core communication (IPC) boundaries mapping across shared SRAM4 (D3 Domain) memory channels for unified status tracking and command dispatch.
- Advanced Motor Control Math: Features complete fixed-point math abstractions for Clarke/Park transforms, flux weakening control blocks, PI current regulators, thermal derating maps, and rotor speed estimation loops.
- Hardware Protection Matrix: Configures real-time monitoring blocks—including DC-link ripple tracking and direct inverter thermal management loops—interlocked straight into a localized fault matrix to protect physical hardware assemblies.
- Bare-Metal Integration: Contains custom vector tables, customized low-level POSIX syscall stubs, and explicit linker map tracking configurations to maximize raw speed without operating system overhead.
Repository Structure
The included distribution archive contains a clean open-source source tree containing the following essential elements:
m7_host_core/: Host application main loop handlers, Ethernet DMA configurations, and Modbus parser drivers.m4_safety_core/: Master unity control script (main_m4.cpp), standalone vector assemblies, and the complete FOC module algorithm library.shared/: Common hardware fault matrix indices, core MPU initialization definitions, and optimized fixed-point mathematical libraries.White Paper.pdf: Comprehensive documentation outlining the underlying control theory, register layouts, and design validation profiles.
Licensing and Terms of Use
This software distribution is managed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0) framework to preserve community-driven academic growth and open-source validation while protecting proprietary hardware intellectual property.