Published August 3, 2026 | Version v1

A 110-170 GHz Phase-Insensitive and PVT-Robust Digital-Step Attenuator with Phase Compensation and Background Step Calibration

  • 1. EDMO icon ETH Zürich

Description

[Abstract]  This work proposes a low-loss digital-step attenuator (DSA) that covers the entire D-band (110-170 GHz) with a tuning range of 15.5 dB and a step of 0.5 dB. Utilizing a multi-stage reflective-type attenuator (RTA) with phase compensation per stage, the DSA simultaneously achieves high precision and low phase variations. Further, a background step-calibration loop is proposed and employed to maintain robust performance with reduced root-mean-square (RMS) and differential nonlinearity (DNL) magnitude errors across process, voltage, and temperature (PVT) variations. The design is implemented in GlobalFoundries 22nm CMOS FD-SOI, achieving a low insertion loss (IL) of 3.5 dB at the reference state at 140 GHz, which can be simply compensated by a single D-band driver stage. The measured RMS magnitude and phase errors remain below 0.19 dB and 2.7respectively across the entire D-band.

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2026_RFIC_Dband_Attenuator.pdf

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Additional details

Funding

European Commission
6G-REFERENCE - 6G haRdware Enablers For cEll fRee cohEreNt Communications & sEnsing 101139155