Verilog HDL-Based Enhanced Detection of Road Lanes and Paint Signs under Noisy Conditions

Accurate detection of road lanes and painted traffic signs is critical for advanced driver assistance systems (ADAS) and autonomous vehicles, especially under challenging environmental conditions such as noise, low illumination, and motion blur. This paper presents a hardware-efficient approach for enhanced detection of road lanes and paint signs using Verilog HDL, targeting real-time implementation on FPfiA platforms. The proposed system integrates noise-resilient preprocessing techniques, including adaptive filtering and contrast enhancement, followed by edge detection and morphological operations to improve feature extraction accuracy. A parallel and pipelined architecture is designed in Verilog to accelerate computation and ensure low-latency processing. To enhance robustness under noisy conditions, the system incorporates threshold optimization and region-based segmentation to distinguish lane markings and painted symbols from background disturbances. The modular design enables scalability and efficient resource utilization, making it suitable for embedded automotive applications. Simulation results demonstrate improved detection accuracy and reliability compared to conventional software-based methods, while achieving high throughput and reduced power consumption. The proposed Verilog-based implementation offers a cost-effective and real-time solution for intelligent transportation systems operating in noisy and dynamic environments.