GAE-GCN: A DEEP GRAPH LEARNING MODEL FOR POWER PREDICTION IN CMOS VLSI CIRCUITS

In very large-scale integration (VLSI) design, power consumption estimation has become something very crucial, having a direct effect on reliability, energy efficiency, management of thermal properties, and other performances at a higher level. With such complementary metal-oxide-semiconductor (CMOS) technology scaling and the complex nature of the integrated circuit, power prediction at an early stage is now of prime importance for design optimization of circuits. Everything with simulation was considered better in terms of power estimation, but it has always been too slow for design iterations. In view of resolving issues in current power estimation systems, this study introduces a novel power estimation scheme using Graph Autoencoder (GAE) combined with Graph Convolutional Network (GCN). Such a model exploits the graph nature of CMOS VLSI circuits, where logic gates and their interconnections are treated as nodes and edges, respectively. The GAE encodes the circuit graphs into low-dimensional latent structural features with preservation of both local and global dependency relationships, while the GCN learns these features to predict power consumption at the circuit level with high accuracy. Initially, gate-level attributes like gate types, flip-flops, inputs, and outputs were considered from the ISCAS’89 benchmark dataset for training and evaluating the model. Experimental results signify the excellent performance of the proposed GAE-GCN model as it has yielded a prediction accuracy with a regression coefficient of 0.9999, RMSE of 0.00010, and a correlation coefficient of 0.999. The results are compared with existing models outlined in the survey for validation purposes. The results comparison indicates that the developed GAE-GCN model outperformed all other models.