Design and Implementation of a Priority-Based Smart Parking System

Efficient parking management is one of the most important demands of the infrastructure of the modern city when the traditional schemes cannot cope with the priority-based distribution of vehicles, which results in time loss and the ineffective use of the space. In this paper, a Smart Multi-Car Parking System with priority-based slot allocation of the Normal, VIP and Emergency vehicles will be discussed in Verilog HDL. The proposed design uses finite state machine (FSM) concept to dynamically control the parking slots depending on real-time priority inputs to optimize parking slots allocation and minimize waiting time of high-priority vehicles. It is modeled and simulated in Xilinx Vivado and the results of the synthesis are analyzed to evaluate performance. The results of simulation prove correct monitoring of vehicle entry and exit, as well as proper distribution of slots among various priority levels without any interferences. A comparative analysis with an already existing parking system based on counters demonstrates that there is the great enhancement of hardware efficiency with the use of LUTs (instead of 100) decreased by 75 percent and registers (instead of 123) decreased by 85 percent. Also, the total power consumption decreases by 1.255 W to 1.04 W, which means increased energy efficiency. The timing analysis will verify that the proposed system has no setup and hold violations and therefore it will be reliable. This design has enhanced functionality, less complex hardware and efficient use of its resources and is therefore very appropriate in smart parking using FPGA in smart transportation systems.