A Jammer-Resilient 2.87mm² 1.28MS/s 310mW Multi-Antenna Synchronization ASIC in 65nm

Abstract—We present the first ASIC implementation of jammer-resilient multi-antenna time synchronization. The ASIC implements a recent algorithm that mitigates jamming attacks on synchronization signals using multi-antenna processing. Our design supports synchronization between a single-antenna transmitter and a 16-antenna receiver while mitigating smart jammers with up to two transmit antennas. The fabricated 65 nm ASIC has a core area of 2.87 mm2, consumes a power of 310 mW, and supports a sampling rate of 1.28 mega-samples per second (MS/s).