Porting the Striped Smith-Waterman Library to RISC-V via LLM-Driven Translation

Manually porting SIMD-optimized libraries across instruction set architectures is costly and error-prone, particularly when optimized kernels rely on architecture-specific idioms. We introduce a fully automated, two-phase LLM-driven pipeline for translating x86 SSE code to native RISC-V Vector (RVV) intrinsics. The first phase produces a functionally correct translation based on sse2rvv, while the second rewrites that translation to exploit RVV's scalable vector-length model. Both phases use an iterative compile-fix loop in which the LLM relies exclusively on compiler and simulator feedback to detect and repair errors. We evaluate the pipeline on the Striped Smith-Waterman (SSW) library, a production-grade genomics kernel. Relative to a manually written naive Smith-Waterman baseline, Phase 1 achieves up to 21.7× speedup, showing that a compatibility-layer-guided translation strategy can serve as an effective foundation for cross-ISA porting. Spike simulation confirms that the Phase 2 transformation remains functionally correct across vector lengths from 128 to 4096 bits. On our target platform with a 256-bit vector length, Phase 2 delivers a further 1.30× speedup. Overall, the fully automated pipeline achieves performance and correctness comparable to those of a manually optimized implementation developed by a human expert with AI assistance.