Fully Parallel Prime Number Search on FPGA Based on the Cyclic Prime Emergence Algorithm

We present a novel FPGA implementation for prime number discovery based on the Cyclic Prime Emergence Algorithm. The architecture employs P parallel programmable oscillators, each corresponding to a specific prime number. Prime detection is achieved through a simple logical OR operation on the oscillator outputs, avoiding division, eliminating memory requirements, and removing sequential dependencies. Each verification step executes in O(1) time, independent of number size or oscillator count. Experimental results from simulation verify the theoretical prediction that the total execution time equals 2 · pP + 1 clock cycles, where pP is the P -th prime number (e.g., for P = 100, p100 = 541). The architecture is fully parameterized and horizontally scalable via daisy-chaining multiple FPGAs.