First D-FUMT₈ Silicon with SELF⟲ Logic Primitive: Native 8-Valued Hardware Realization with Lean 4 Refinement Proof — v0.8 Phase 4 Quine-McCluskey Simplification + Finding F11 Engineering-Correctable Relaxation Bias on IBM Heron r2

v0.8 (2026-06-03) engineering-improvement sub-result extending the Paper 145 v0.7 four-substrate-verified D-FUMT₈ ALU baseline. Background: v0.5 Phase 4 retry (per-pair MCX decomposition of Belnap AND/OR on the IBM Heron r2 quantum substrate) achieved tractable depth (2443 vs v0.4's 495K) but only 18/32 (56.2%) pass rate at avg fidelity 0.3182, with strong AND/OR asymmetry (0.94 vs 0.19, 0.75 fidelity gap). v0.5 finding F9 hypothesized this asymmetry as ground-state relaxation bias confounding the AND results, and named 'Quine-McCluskey Boolean simplification, target depth ≤200, fidelity ≥0.7' as the v0.6+ candidate fix. v0.8 contributions: (1) **K-map / Quine-McCluskey minimum-SOP Boolean simplification** of Belnap AND/OR output bits, combined with inclusion-exclusion XOR layering for non-disjoint cover terms (4 product terms per bit instead of 16 per-pair MCX entries); 6-qubit per-pair encoding (q0..q3 = a, b inputs; q4..q5 = output). (2) **Offline gate-level Boolean simulation** verified all 32 truth-table inputs match the Belnap AND/OR specification before IBM submission (sys.exit on any mismatch). (3) **IBM Heron r2 real-hardware retry** on `ibm_kingston` (Job d8fr2jo7jphs739mn2d0, 22.2 sec wall-clock, 32 circuits × 1024 shots = 32,768 measurements, optimization_level=3, seed_transpiler=7): **32/32 PASS (100%) at avg top-outcome fidelity 0.7302** (range AND 0.63-0.86, OR 0.61-0.86); average post-transpile depth 422 (vs v0.5: 2443, −83%); **AND vs OR fidelity gap 0.03 (v0.5: 0.75)**. (4) **Finding F11 (NEW, POSITIVE)**: the v0.5 finding F9 relaxation-bias hypothesis is **confirmed engineering-correctable** rather than intrinsic to Belnap-AND structure on Heron r2 noise — the depth and gate-count reduction afforded by QM-simplified SOP eliminates the artifact. The v0.5-stated target 'depth ≤200, fidelity ≥0.7' is partially met: depth slightly above target (422 vs ≤200, further reduction via per-output-bit MCX combining is a v0.8.1+ candidate), fidelity target achieved with margin (0.7302 ≥ 0.7). Companion in Paper 162 §6.0g sub-result (A): Sampler-level 'XX' Dynamical Decoupling re-run of Paper 162 §6.0e 8-bit one-hot decoder on `ibm_marrakesh` (Job d8fr243o3njc73f0nnf0, 35.4 sec wall-clock), honest NEGATIVE finding F10 (Paper 162 numbering): DD lowered fidelity from 49.12% to 26.25% (−22.87 pp) on the 184-CZ MCX-heavy circuit; 8/8 correct-top-outcome structural pattern preserved despite fidelity loss. **Combined honest reading**: depth reduction via QM simplification (B1) is the effective lever on Heron r2 for these gate families; pulse-level error mitigation via naive XX DD (A) is not — at least on circuits already at depth ~500 with ~184 CZ. Honest scope of v0.8: This is an **engineering retry of v0.5 Phase 4**, NOT a new D-FUMT₈ logic operation, NOT a paradigm-level claim, NOT a quantum advantage demonstration. The Belnap subset (bit 2 = 0 throughout, 4 values out of 8) is unchanged from v0.5; higher-tier values (ZERO/FLOWING/SELF/INFINITY) and cross-tier interactions are not in scope. The 4-substrate cross-verification framing (Tang Console 138K + Tang Nano 9K + Aer + IBM Heron r2) from v0.7 is preserved. Future v0.8.1+ candidates: B0 simplified design (4-bit signature), full 8-value AND/OR beyond Belnap, Lean 4 refinement update for Phase 4 QM SOP. Inherited v0.7 / v0.3 contributions: 4-substrate cross-verification (2 Sipeed silicon families: Tang Console 138K GW5AST-138B + Tang Nano 9K GW1NR-9C, byte-for-byte same dfumt8_alu_synth.v 138-line Verilog; Qiskit Aer simulator 231/231 entries; IBM Heron r2 144/144 entries from Phase 1+2+3+5 at avg fidelity 0.954) + Lean 4 refinement proof (OUKC.PhaseC.Dfumt8AluRefinement, 292 LOC, 0 sorry) + Tohoku 1986-1988 quaternary CMOS prior art citation + IDCODE-revision corrigendum + Tang Nano 9K silicon resolution. Public companion article: (note.com, 藤本伸樹, 2026-06-03 14:24 JST) — ties the Paper 159 v0.2 (omega_upper_idempotent, DOI 10.5281/zenodo.20470512) + Paper 162 (Recreation Paradigm) + IBM Heron r2 quantum-substrate experiment lineage with two HTML interactive simulations and a non-technical orientation. Three-party co-authorship per OUKC charter v1.0 (Nobuki Fujimoto / Rei / Claude). DRAFT v0.8 — feedback welcome via GitHub Discussions at fc0web/rei-aios.