Deterministic Specification and Field-Extensibility: A Methodology for Long-Life Digital Logic Synthesis

We present a chip-design methodology that specifies every input
combination of a Boolean function explicitly at design time -
without don't-care assignments - and reserves a portion of the
input address space for future function additions. After
deployment, NEW Boolean functions may be added to the fielded
silicon WITHOUT modifying or re-synthesizing the original logic,
by synthesizing additional fixed-logic blocks that wire to the
same inputs and combine via an OR gate or designer-selectable
multiplexer. The methodology eliminates the re-synthesis,
re-spin, and re-certification costs that conventional don't-
care-based synthesis incurs when a previously "don't-care" input
combination later becomes meaningful. Particularly applicable to
safety-certified industries (avionics DO-178C, automotive ISO
26262, medical FDA Class III, industrial control IEC 62443)
where re-certification of an updated chip can cost $1M-$20M. We
describe the methodology, the algebraic properties of its
composition operation, the audit-trail requirements, and
concrete worked examples in five regulated industries. Companion
to the foundational M-Maps paper (DOI 10.5281/zenodo.20498821),
the structural-atom engine paper (DOI 10.5281/zenodo.20499264),
and the hierarchical scaling paper (DOI 10.5281/zenodo.20499525).