Paper MDE v1.1

Paper MDE v1.1 provides the complete Register-Transfer Level (RTL) specification of the Master Dynamics Equation (MDE) of Ontological Resolution Theory (ORT). Each carrier node holds a 133-bit state register decomposed into two typed sectors: an 83-bit potential sector (P) carrying topological phase structure, and a 50-bit actual sector (A) carrying executable amplitude. Both sectors obey the discrete Boolean d'Alembertian over F_2, with the actual sector receiving a topological source term h(P) from the potential sector. Key results: (1) Actual-sector update rule: the A-sector obeys a P-modulated F_2 wave equation — the discrete Boolean d'Alembertian with potential-sector source term. This is the exact F_2 analogue of the sourced wave equation □A = J, where J = h(P) is a topological current density. (2) Phase accumulator throttle: carrier throttling is implemented by a purely integer carry register that realizes the canonical ORT throttling relation Theta_i = K_cell / (K_cell + rho_i) exactly, using only integer addition and comparison. No division. No floating-point arithmetic. The accumulator is proven to be unconditionally T-invariant: the active/throttled state of any past tick is recoverable from the carry register value alone, without storing additional flags (carry < K implies active; carry >= K implies throttled). (3) Full single-tick microcode: the complete RTL specification of one tick for one node is given as a deterministic sequence of approximately 2000 Boolean operations. All operations are Boolean or integer. Zero floating-point arithmetic inside the tick loop. (4) Reversibility: Branch 1 (standard evolution) is proven perfectly reversible. Branch 2 (Node Genesis) is intentionally irreversible, modeling asymmetric cosmic file growth. (5) Boolean d'Alembertian: both sectors are shown to implement the discrete F_2 wave operator — the exact Boolean analogue of the relativistic d'Alembertian □ over the FCC graph. The specification is directly implementable in CUDA/C++ or FPGA/ASIC synthesis. Memory per node: 26 bytes. A 16M-node simulation fits in 416 MB of GPU memory. Part of the ORT Canon corpus. Canon version: v31.1. Supersedes: Paper MDE v1.0.