Empirical Evidence of Topology-Matched Cyclic Symmetry Signatures on Native Heron Heavy-Hex Architectures

We report a preliminary hardware study of an N = 12 periodic transverse-field Ising
model (TFIM) executed on a native 12-qubit heavy-hex plaquette of IBM Heron hardware.
By mapping the logical periodic boundary condition directly onto the processor’s native
topology, we eliminate routing overhead and obtain zero-SWAP transpilation on the selected
cycle.
The study combines exact local diagonalisation, symmetry-preserving ring ansätze, bound-
before-transpile compilation, native fractional-gate execution, and single-PUB estimation of
the Hamiltonian energy together with parity and local symmetry witnesses. We compare
deeper (p = 3) and shallower (p = 2) variational settings under matched hardware-oriented
execution conditions, including fractional-gate transpilation and dynamical decoupling where
applicable.
Our principal empirical result is a consistent depth-versus-noise tradeoff: a shallower
p = 2 circuit produced better hardware energy and parity than a deeper p = 3 circuit,
despite the deeper ansatz being superior in ideal local simulation. We interpret this as
evidence that, on present-generation noisy hardware, reduced interaction cost and topology-
matched execution can outperform greater variational expressivity.
We do not claim ground-state certification from the present runs. Instead, we present
these results as preliminary empirical evidence of topology-matched cyclic symmetry sig-
natures under noise, together with a reproducible workflow for native heavy-hex plaquette
experiments.