Power-Optimized Verilog Based Architecture for Real Time Bus Ticketing System

Efficient ticketing systems are essential to improve the speed and convenience of public transportation. Traditional manual ticketing methods often result in delays and inefficiency during passenger boarding. Automated ticketing systems implemented using hardware solutions can significantly reduce processing time and improve the operational efficiency. This study aims to design and implement a power-optimized automatic bus ticketing system using Verilog Hardware Description Language (HDL) and deploy it on a field programmable gate array (FPGA) platform. The proposed system was developed using Verilog HDL and implemented in a Xilinx Vivado design environment targeting an Artix-7 FPGA. The architecture consists of four main modules: Ticket selection, rupees calculation, return processing, and display interface. To reduce dynamic power consumption, flipflop-based clock gating was incorporated into the design. Functional simulations are conducted in Vivado to verify the accuracy of each module. In addition, power, area, and timing analyses were conducted to compare the conventional architecture with the optimized clock-gated implementation. Simulation and synthesis results demonstrate that the clock-gated design achieves noticeable power reduction while maintaining efficient resource utilization and timing performance. The proposed FPGA-based automatic bus ticketing system provides a fast, reliable, and power-efficient solution suitable for real-time public transportation applications. This architecture also offers scalability to future intelligent fare-collection systems.