An Assessment of MAC Unit Architectures for Digital Signal Processing Applications
Authors/Creators
- 1. Dr. Rohan K. Patel, Department of Electrical Engineering, University of Illinois at Urbana-Champaign, 306 N. Wright St, Urbana, IL 61801, USA
Description
In today's smart and digital world, the brisk encroachment in science and technology has boosted up the requirements for Digital Signal Processors (DSPs) which are having superior computing efficiency, high speed and low power consumption along with real time application feasibility. For designing any Digital Signal Processors or other applications related to signal processing, Multiply-Accumulate (MAC) unit is one of the most vital blocks of processor. The performance of the designed MAC unit in turn evaluates the eventual whole and sole performance of any system of application. Hence, the speed, power consumption, area etc. have been the key spots of apprehension in progression of a variety of MAC architectures. This paper facilitates a generic survey on various techniques utilized to implement MAC units to enhance the performance. The presented survey paper finally promotes the researches to implement an efficient MAC architecture for applications related to digital signal processing domain. Key words: Digital Arithmetic, Multiply-Accumulate (MAC) Unit, On-Silicon Area, Power Consumption, Mean Square Error (MSE). ________________________________________________________________________________________
Files
JCE-v11-I01-006.pdf
Files
(308.9 kB)
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